This invention relates to input/output (I/O) controllers for use in digital data processing systems for transferring data between a host processor and one or more peripheral units or I/O units. More particularly, this invention relates to I/O controllers which employ microprocessors for supervising the data transfer activities.
A primary purpose of the present invention is to provide a high performance I/O controller which is very flexible and versatile in terms of the kinds and numbers of tasks it can perform and in terms of the kinds and numbers of I/O units which it can handle. Other objectives are to provide: (1) an I/O controller to which various kinds and combinations of present and future I/O units can be attached in a relatively simple and straightforward manner; (2) an I/O controller which can handle a goodly number of different data transfer tasks in a very efficient and highly concurrent manner; (3) an I/O controller, which is capable of offloading various programming and data processing functions from the host processor; and (4) an I/O controller which never returns a "controller busy" signal to the host processor.
These objectives are realized to a major extent by providing a microprocessor based I/O controller configuration wherein the microprocessor is allowed to function as a general purpose processor and not as a limited purpose I/O controller. Among other things, I/O units (or their associated device controllers) are connected to the I/O controller by simply attaching them to the microprocessor I/O bus. Thus, the microprocessor can transfer data to and from the I/O units in its normal manner.
These objectives are further realized by employing a dual port random access storage mechanism to provide the data transfer interface between the microprocessor I/O bus and the I/O channel bus of the host processor to which the I/O controller is connected. One port of this storage mechanism is connected to the host processor channel bus and the other port is connected to the microprocessor I/O bus. The construction of the I/O controller is such that the microprocessor thinks that this dual port storage is its own private random access storage unit. Nevertheless, this dual port storage mechanism can be accessed directly by the host processor and the host processor can thereby transfer data to or from the dual port storage mechanism. Thus, the dual port storage is a shared storage unit which is shared by both the microprocessor and the host processor but with the host processor storage accesses being transparent to the microprocessor.
A further feature is the inclusion in the I/O controller of a direct memory access (DMA) controller which is in addition to the microprocessor and which is used to provide a high speed cycle steal mode of data transfer between the dual port controller storage unit and the main storage unit of the host processor. In particular, the DMA controller includes a first channel for supplying host processor main storage addresses to the host processor and a second channel for supplying controller storage addresses to the dual port storage mechanism. These DMA channels are operated in unison to bring a word of data out of the host processor main storage unit and to write in into the addressed location in the dual port storage unit or, conversely, to bring it out of the dual port storage unit and to write it into the addressed location in the host processor main storage unit. Circuitry is provided for interleaving the previously considered host processor direct storage access data transfers with these DMA controller controlled cycle steal data transfers. Thus, two different modes of data transfer are provided between the host processor and the I/O controller, with these modes being interleaved to provide a minimum of delay and interference with one another. Among other things, this enables new I/O commands to be received from the host processor at the same time that the I/O controller is engaged in the cycle stealing transfer of a block of data to or from the host processor main storage unit.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.